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FPGA-IP-Cores

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FPGA-IP-Cores

TSN

This is a PCIe NIC card designed to work on a board/computer supporting 4 lane PCIe connector. It supports PCIe Gen1 speeds, Gigabit rate over Ethernet ports

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10G/40G Ethernet

Full-duplex MAC, fully compliant to IEEE802.3. 64 bit wide data bus for 10G and 128 bit wide bus for 40G and 25G. Implements Padding, FCS, error handling and MIB counters

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sFPDP

Vibhatsu's SFPDP Logic core meets ANSI-VITA 17.1- 2003 [and ANSIVITA 17.1-2015], designed for FPGA based targets

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TCP Offload

TCP Offload engine implements all the TCP/UDP processing in FPGA logic thus reducing the processing overhead by the system/host.

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JESD

The JESD204C FPGA IP core is a high-speed multi-lane data interface for ADCs and DACs. It i fully compliant to JEDEC standard JESD204C.1 [Dec2021].

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1553

The IP-Core 1553 BRM provides a complete, MIL-STD-1553 Bus Controller (BC), Remote Terminal (RT), or Monitor Terminal (MT).

Download PDF 6